Interface Trapping in (2¯01) Β-Ga2o3 MOS Capacitors with Deposited Dielectrics

The electrical properties of interfaces and the impact of post-deposition annealing have been investigated in gate oxides formed by low pressure chemical vapor deposition (LPCVD SiO2) and atomic layer deposition (Al2O3) on (2¯01) oriented n-type β-Ga2O3 single crystals. Capacitance-voltage based methods have been used to extract the interface state densities, including densities of slow ‘border’ traps at the dielectric-Ga2O3 interfaces. It was observed that SiO2-β-Ga2O3 has a higher interface and border trap density than the Al2O3-β-Ga2O3. An increase in shallow interface states was also observed at the Al2O3-β-Ga2O3 interface after post-deposition annealing at higher temperature suggesting the high temperature annealing to be detrimental for Al2O3-Ga2O3 interfaces. Among the different dielectrics studied, LPCVD SiO2 was found to have the lowest dielectric leakage and the highest breakdown field, consistent with a higher conduction band-offset. These results are important for the processing of high performance β-Ga2O3 MOS devices as these factors will critically impact channel transport, threshold voltage stability, and device reliability.