DCR and crosstalk characterization of a bi-layered 24 × 72 CMOS SPAD array for charged particle detection

This paper presents the results from the crosstalk and dark count rate (DCR) characterization of a 24 × 72 single photon avalanche diode (SPAD) array, fabricated in a 150 nm CMOS technology. The chip under test consists of a dual layer detection system developed in view of applications to charged particle tracking. A three step procedure, used for the crosstalk characterization, is presented. The crosstalk probability, taking place in 5 × 5 sub arrays built around noisy pixels, has been computed. Eventually, random telegraph signal (RTS) fluctuations in DCR, at different bias conditions, are briefly discussed.