Design and Analysis of a Type-II Sampling PLL with Automatic Frequency and Phase Calibrations Achieving 0.62- $\mu$ S Locking Time
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS（2025）
Key words
Frequency locked loops,Time-frequency analysis,Voltage-controlled oscillators,Transient analysis,Microelectronics,Calibration,Very large scale integration,Clocks,Tuning,Automatic frequency and phase calibration (AFPC),fast lock,figure-of-merit (FoM),low-jitter,phase-locked loop (PLL),phase noise,phase noise
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