Effect of Boro-Silicate Glass (BSG) Gate Dielectric with Antimony Surface Doping on Channel Transport of 4H-SiC Mosfets

In this work, we investigate the effect of Boro-silicate glass (BSG) gate dielectric in conjunction with Antimony (Sb) surface doped channels of lateral 4H-SiC MOSFETs. It has been reported that BSG gated 4H-SiC MOSFETs have a high channel mobility of ~100 cm2/V∙s for a wide range of surface transverse electric fields along with a large threshold voltage VT of ~5V in lightly doped p-epitaxial layers [1,2]. For vertical power MOSFETs with heavily doped p-wells, it is expected that BSG would cause an even further increase of VT (~10 V) which would be undesirable. Therefore in this work, our goal for combining the Sb surface doping process (demonstrated in our earlier works [3,4] and presented at ECSCRM 2014 [4]), with BSG gate dielectric was two-fold: (i) Tune VT to adequate value with high sub-threshold slope. (ii) Achieve high low-field channel mobility by Sb counter-doping while retaining the high-field mobility characteristics of BSG. The results from our experiments indicate that these goals were achieved. The 'Sb+BSG' process results in significant improvement of both low-field channel mobility to ~180cm2/V∙s (due to addition of Sb surface doping) and high-field channel mobility to ~90 cm2/V∙s (due to the BSG gate dielectric) along with a tuned threshold voltage of ~2V and a steeper sub-threshold slope. Lateral MOSFETs were fabricated on the Si-face of p-type 4H-SiC epitaxial layers doped at ~1x1016cm-3. Sb was implanted in the channel region with 80 keV at room temperature with dose of 2.5x1013cm-2, which results in a Gaussian profile with a depth of around 30nm below the surface of SiC. This was followed by post-implantation activation annealing at 1650°C using a graphitic carbon cap layer. Next, dry oxidation at 1150°C for 10 hours was performed followed by post-oxidation annealing using a planar diffusion source (Techneglas, GS-139) composed of boric oxide (B2O3) in a gas mixture of Ar (50sccm) and O2 (5sccm) at 950°C for 30 mins. Samples that received only boron annealing are referred to as 'BSG only' and samples underwent both Sb counter-doping and boron annealing are referred to as 'Sb+BSG'. Results for these samples are compared with standard NO-annealed devices in Table Ⅰ. The SIMS result in Fig. 1 shows B distributes throughout the oxide with a concentration of ~1x1022cm-3 and decreases as it reaches SiC. Threshold voltage and sub-threshold slope were characterized by Id-Vg measurement at room temperature and field-effect mobility was extracted from the transconductance of Id-Vg curve. Linear and log scale of Id-Vg curves in Fig. 2 and Fig. 3 demonstrate that 'Sb+BSG' tunes the threshold voltage to a more desirable value of ~2V along with a better sub-threshold slope than standard NO annealing. Fig. 4 shows a significant mobility improvement for 'Sb+BSG' at both high field due to the BSG passivation effect and low field due to the Sb counter-doping effect with a peak value of ~180cm2/V∙s compared to 'BSG only' with a peak mobility of ~140cm2/V∙s. In order to investigate the boron passivation effect on interface traps, C-V and constant capacitance deep level transient spectroscopy (CCDLTS) measurements were performed on the companion BSG capacitors. The interface trap density of 'NO' was determined to be ~2.5 times higher than that of 'BSG' for very shallow energy traps (<0.2 eV) from C-V measurements and ~1.5 times higher for the energy trap distributions centered at 0.15 eV and 0.39 eV by CCDLTS, as shown in Figs. 5 and 6. The mechanism of boron passivation has been suggested to be oxide stress relaxation by the reduction of required oxygen bonds due to the occupation of Si site by B [5]. In this presentation, further details of the nature of transport and mobility behavior in BSG gated channels will be presented as a function of temperature. References [1] D. Okamoto, M. Sometani, S. Harada, R. Kosugi, Y. Yonezawa, and H. Yano, IEEE Electron Device Lett. 35, 12 (2014). [2] T. Isaacs-Smith, Y. Zheng, C. Jiao, A. C. Ahyi, and S. Dhar, 2016 MRS Spring Meeting & Exhibit, Phoenix, Arizona, 4 (2016). [3] A. Modic, G. Liu, A. C. Ahyi, Y. Zhou, P Xu, M. C. Hamilton, J.R Williams, L. C. Feldman, and S. Dhar, IEEE Electron Device Lett.35, 894 (2014). [4] A. C. Ahyi, A. Modic, C. Jiao, Y. Zheng, G. Liu, L. C. Feldman, and S. Dhar, Materials Science Forum, Vols. 821-823, (2015) pp. 693-696. [5] Xiao Shen, and Sokrates Pantelides, 11th annual SiC MOS workshop meeting, UMD College Park, August 15, 2016. Figure 1